The present invention disclosed herein relates to memory access devices, and more particularly, to memory access devices including multiple processors accessing a specific memory.
An embedded system includes a processor and a memory device that stores data accessed by the processor. A dynamic random access memory (DRAM) device is used as the memory device of the embedded system. Typically, an embedded system uses a DRAM device as a system memory.
In an embedded system, a processor communicates with a system memory through a processor bus and a memory controller. The processor generates a memory access request. The memory access request includes a memory command (e.g., a read or write command) and an address that indicates a read location of data/commands or a write location of data/commands.
The memory controller generates not only row/column addresses but also suitable command signals. The memory controller applies address/command signals to the system memory through a system bus. The system memory transmits data, corresponding to the commands or addresses, to the processor through the system bus.